You’ve been using VHDL for years (or just beginning), and you hear sometimes that you should abandon it right away and switch to SystemVerilog (sometimes noted “SV” in the following). But you may also hear horror stories about people discouraged by the breadth and complexity of SystemVerilog.
At ALSE, we’ve been there, done that.
As a 23 years-old French Design House, with a majority of European customers, our main design language has been VHDL, though we had our share of Verilog designs for some customers. We still have a slight preference for VHDL against Verilog at least for design, but we’ve convinced ourselves long ago that SystemVerilog was a clear long-term winner.
And quite logically, for our complex IPs, we have switched already to SystemVerilog. If you attend one of our Trainings, you’ll see how enthusiastic we are about using SystemVerilog !
Let’s see some facts about this “Language War” and bust some myths.
If you are an ASIC designer, then you already master Verilog ! Because Verilog is absolutely compulsory in ASIC flows.
So we are supposing you are an FPGA Designer using VHDL.
Any designer should master both VHDL and Verilog
It’s not a new fact ! Neither VHDL nor Verilog did grab all the shares and we still see both being used throughout the world and the various industries. If you receive an IP, it can be in Verilog or VHDL (and now SystemVerilog for recent ones).
If you only master one of the two languages, you have no excuse ! With our instructor-led training, we teach Verilog to VHDL designers in just one (intense) day (count two days for a self-paced training). That all it takes. So it’s clearly a modest investment, and it does allow you to be at ease with HDL code in both languages.
Do I need Verilog before SystemVerilog ?
SystemVerilog is a superset of Verilog, which it does encompass. So if you start from scratch, you would need in any case to learn the Verilog concepts before learning all that has been added on top of it.
Another reason to start with Verilog, then add SystemVerilog extensions, is that it will help you understand how to write code that remains compatible with the Verilog tools and flow. In many cases, you may need to stay within the Verilog language boundaries (because of some tools).
Isn’t SystemVerilog a HUGE language ?
Yes. With a 1815 pages LRM and (at least) FIVE complex languages rolled into one, it’s hard to disagree ! By the way: thanks to Accellera, this IEEE LRM is available free of charge !
But this doesn’t mean you have to learn ALL of it at once ! The trick is to learn (and master) exactly what you need and not more (well, it’s already quite significant). You’ll see that you can take advantage of 80% of the languages benefits with only 20% of the efforts, and that’s exactly what us, Engineers, love to hear.
And what about UVM ?
UVM is a completely different story (than SystemVerilog) ! You must learn SV, but you might want to adopt UVM for Verification.
The only relationship is that UVM is based on SystemVerilog Verification Classes, so you can’t learn UVM without learning SystemVerilog including its OOP part.
But clearly, you can take advantage of SystemVerilog while not using UVM.
We will dedicate a separate article to UVM, just note at this point that it’s way harder to learn and master than SystemVerilog !
The Best Path to SystemVerilog
After applying it to ourselves and teaching it to hundreds of Engineers, we have accumulated a lot of success in the following approach :
- Learn “Verilog for VHDL Users” if necessary (1 or 2 days)
- Learn “SystemVerilog for Design” (3 days ILT) … and stop here at least for a while !
You will master :
- Coding style for efficient RTL while taking advantage of the superior features of SV.
- Interfaces (which are absolutely suitable for synthesis !)
- SystemVerilog Assertions !
This is a fantastic way to enhance your code and ease the verification.
- Advanced semantic for safer code and more efficient logic optimization
- Better expressiveness
- How to avoid usual pitfalls
- How to work around some irritating “features”
- How to take advantage of some tools to secure the code But the highest gains in productivity will come from the Verification features of SV.
- ABV : using SVA (SV Assertions) for both RTL and Verification modules.
Note that Assertions also provide free functional coverage !
- Test benches (aka test fixtures) and behavioral models.
for both, SV offers a tremendous improvement over VHDL.
- Stimuli Generation (Constrained Random)
- Functional coverage (from SVA and covergroups)
- Cover-driven simulation to minimize simulation time while ensuring that coverage goals are met.
- Enhanced data types to facilitate Modelling and Verification.
Yes, we can teach this -and more- in just 3 days Instructor-led Training.
Reasonable Pain, Huge Gains !
You can augment radically your productivity as well as the quality of your designs, and make your Verification fly.
You’ll need :
- Assertions (SVA) -everywhere !-
- Enhanced Synthesis constructs
- Enhanced Data types
- Constrained Random
- Cover-driven simulation
- Basics of Enhanced Process control
- And maybe a bit of DPI
- Understand how to enhance your design & verification Methodology.
It’s often just not an option
Verification is more and more demanding and certification authorities -for the first time- start mentioning explicitly SystemVerilog (and UVM) as the right tools to achieve the certification goals. One of the magical words is “Functional Coverage”. Gone are the days when the famous “100% statement coverage” made the quality dept guys happy.
And if your project deserves the use of formal tools, you’ll remember that most of them take SVA as input !