We have developed an optimized IP that implements the same functionality as the PCA 9556 and 9557, with the ability to handle more ports and to fit in very small Programmable devices (one implementation fits in an 240 Macrocells CPLD).
The function performed by these devices is :
This function is not very complex, so we deliver this IP in source code mode so the user can freely customize and re-use it.
When the original device had one port, our IP can have many 8-bits ports, this is a parameter in the IP core.
Moreover, the Voltage Levels and I/O standards will be those available on the FPGA. While being potentially an issue if 5V is required, it is usually and advantage when other levels are required.
A Demonstrator is available.