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These utilities are free to use, with the usual disclaimer above: use this at your own risk.

SystemVerilog definition files for Crimson Editor.
unzip into Crimson’s base installation directory.

Verilog RTL ROM Generator
This Tcl/Tk utility reads in a memory contents file in Intel-Hex format and produces synthesizable Verilog code for the ROM.

VHDL Quick Reference sheet.
Standard RTL & Test bench templates and Numeric_std reminder, all in one sheet.

Numeric_std cheat sheet.

Utility (Tcl) to capture the current Date & Time information (“wall clock time”) from within a VHDL simulation. © ALSE, for use with ModelSim. Your batch simulation can record start and end time in the VHDL output. Great also for simulation run-time optimization.

Document download