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Type Titre Description Poids Rattaché à
Format: PNG Untitled 1.1 MiB REFLEX CES DevKits
Format: PNG Untitled 2.1 MiB REFLEX CES DevKits
Format: PNG Untitled 853.3 KiB REFLEX CES Stratix 10 boards
Format: PNG Untitled 1.2 MiB REFLEX CES DevKits
Format: PNG Untitled 1.1 MiB REFLEX CES Stratix 10 boards
Format: PNG Untitled 999.6 KiB REFLEX CES Stratix 10 boards
Format: PNG Untitled 42.5 KiB Aurora 64B/66B IP Core
Format: JPEG Untitled 53.2 KiB Happy New Year
Format: PNG ADM Block Diagram 72.1 KiB ADM - Max 10
Format: JPEG ADM Max 10 Module 220.2 KiB ADM - Max 10
Format: JPEG AES member 17.6 KiB Digital Audio
Format: PNG Agilex 257.3 KiB Designing for Stratix 10 & Agilex FPGAs
Format: JPEG ALSE HighSpeed (dual-core) JPEG Encoder 90.3 KiB High-Speed JPEG Video Encoder
Format: JPEG ALSE is a Lattice Partner 11.5 KiB Lattice
Format: JPEG Altera Design Partner 159.5 KiB History
Format: PNG Altera Original Logo 7.5 KiB History
Format: PNG Altera Partner 58.9 KiB Altera
History
Format: JPEG AntiCopy 41.9 KiB Copy Protection
Format: JPEG Arrow AXE5 Eagle board 45.5 KiB Agilex 5 FPGAs
Format: JPEG Arrow-Trenz AXE5000 Agilex 5 board 190.2 KiB Agilex 5 FPGAs
Agilex 5 FPGAs
Format: PNG Aurora Typical Application 46.1 KiB Aurora 8B/10B IP Core
Format: JPEG Aurora64 Architecture 91.8 KiB Aurora 64B/66B IP Core
Format: JPEG AVDB Board 136.2 KiB AVDB - Video Board (Obsolete)
Format: JPEG Avnu 27.1 KiB AVB MILAN
What is AVB MILAN ?
Format: JPEG Avnu Alliance 11.2 KiB Digital Audio
Format: PNG Block diagram of Achilles Arria 10 SoC SOM 44.4 KiB REFLEX CES DevKits
Format: PNG Block diagram of Alaric Arria 10 SoC 63.1 KiB REFLEX CES DevKits
Format: PNG Block diagram of Attila Arria 10 GX 49.6 KiB REFLEX CES DevKits
Format: PNG Block diagram of Sargon Stratix 10 GX SX 91.4 KiB REFLEX CES Stratix 10 boards
Format: PNG block diagram of the COMXpress 53.3 KiB REFLEX CES Stratix 10 boards
Format: PNG block diagram of the XpressGX/SX S10 82.8 KiB REFLEX CES Stratix 10 boards
Format: JPEG BlockDiagram 52.9 KiB MachXO5 Example Design
Format: JPEG Colorlight board 1.5 MiB LiteX and Lattice FPGAs
Format: PNG Demo Architecture 28.8 KiB Aurora 64B/66B IP Core
Format: JPEG Design Services 33.7 KiB ALSE: Advanced Logic Synthesis for Electronics
Format: GIF Ethernet Solutions 9.2 KiB ALSE: Advanced Logic Synthesis for Electronics
Format: PNG Examples of ALSE Aurora 64 IP on Lattice FPGAs 5.8 KiB Aurora 64B/66B IP Core
Format: PNG Examples of ALSE Aurora 64 IP on Microchip FPGAs 10.7 KiB Aurora 64B/66B IP Core
Format: GIF Free IPs 8.8 KiB ALSE: Advanced Logic Synthesis for Electronics
Format: PNG GraDiEn 32.6 KiB Graphic Display
Format: JPEG HPAPB Stratix V board 420.2 KiB HPAPB - Stratix V
Format: JPEG HPBB Board 73.1 KiB HPPB - Stratix IV (Obsolete)
Format: PNG hyper read 34.9 KiB HyperRam Memory Controller
Format: PNG hyper write 30.9 KiB HyperRam Memory Controller
Format: JPEG Indeex: Industrial Ethernet Extension Board 68.9 KiB IndEEx
Format: JPEG Industrial Ethernet standards Cycle Time 43.7 KiB Ultra Low Latency Network
Format: JPEG Intel Agilex 5 FPGA E-Series 065B Development Kit - Premium 207.6 KiB Agilex 5 FPGAs
Format: PNG Intel FPGA Design Center 42.3 KiB Altera
History
Format: GIF Intellectual Properties 12.4 KiB ALSE: Advanced Logic Synthesis for Electronics
Format: JPEG La Scala Carrier Board (without AVB64M module) 1.1 MiB La Scala !
Format: JPEG LaScala : MILAN SoM Carrier Board 254 KiB AVB MILAN
What is AVB MILAN ?
The ALSE AVB Milan IP
Format: JPEG LVDS 500Mb/s demo using 2 x BeMicroMax10 boards 99.3 KiB High Speed LVDS communication
Format: JPEG MachXO5-NX board 46.4 KiB MachXO5 Example Design
Format: JPEG MachXO5T-NX evaluation board 49.4 KiB MachXO5 Example Design
Format: JPEG MILAN 204.1 KiB AVB MILAN
What is AVB MILAN ?
Format: JPEG Milan AVB System On Module 63.1 KiB AVB MILAN
What is AVB MILAN ?
The ALSE AVB Milan IP
Format: JPEG Network (ring) Topology 37.7 KiB Ultra Low Latency Network
Format: JPEG Nina extending the DE0-nano 123.8 KiB Nina
Format: PNG SelectBadge 94.5 KiB
Format: JPEG SelectBadge 92 KiB
Format: JPEG SelectBadge 92 KiB
Format: JPEG SSRAM no bus latency waveform 196.3 KiB Synchronous SRAM (SSRAM) Controller
Format: JPEG Synchronous Edge Detector 16.1 KiB VHDL templates
Format: JPEG Tower of DE2-115 192.6 KiB Ultra Low Latency Network
Format: PNG Typical application 18.1 KiB Aurora 64B/66B IP Core
Format: JPEG Formations en France 28 KiB ALSE: Advanced Logic Synthesis for Electronics
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