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Untitled |
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1.1 MiB |
REFLEX CES DevKits
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Untitled |
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2.1 MiB |
REFLEX CES DevKits
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Untitled |
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853.3 KiB |
REFLEX CES Stratix 10 boards
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Untitled |
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1.2 MiB |
REFLEX CES DevKits
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Untitled |
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1.1 MiB |
REFLEX CES Stratix 10 boards
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Untitled |
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999.6 KiB |
REFLEX CES Stratix 10 boards
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Untitled |
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42.5 KiB |
Aurora 64B/66B IP Core
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Untitled |
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53.2 KiB |
Happy New Year
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10GEDEK Datasheet |
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232.8 KiB |
10G Ethernet for FPGAs
|
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ADM Block Diagram |
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72.1 KiB |
ADM - Max 10
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ADM DataSheet |
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322.5 KiB |
ADM - Max 10
|
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ADM Max 10 Module |
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220.2 KiB |
ADM - Max 10
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AES member |
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17.6 KiB |
Digital Audio
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Agilex |
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257.3 KiB |
Designing for Stratix 10 & Agilex FPGAs
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ALSE 10GEDEK IP Reference Design on Polarfire |
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701 KiB |
10G Ethernet on Polarfire
|
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ALSE : a Short Presentation |
ALSE Short presentation |
2.9 MiB |
ALSE: Advanced Logic Synthesis for Electronics
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ALSE AntiCopy solution |
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578.4 KiB |
Copy Protection
|
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ALSE Aurora 64B/66B Reference Design for Polarfire |
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596.4 KiB |
Aurora 64B/66B IP Core on Polarfire
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ALSE Aurora 8B/10B Datasheet |
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439.6 KiB |
Aurora 8B/10B IP Core
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ALSE Aurora64 Agilex5 Demo User Guide |
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3.2 MiB |
Aurora 64B/66B IP Core
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ALSE Aurora64 Demo on Efinix Titanium |
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1.2 MiB |
ALSE Aurora 64B/66B on Efinix
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ALSE Aurora8b10b on Efinix Titanium : Demo User Guide |
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1.6 MiB |
ALSE Aurora 8B/10B on Efinix
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ALSE HighSpeed (dual-core) JPEG Encoder |
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90.3 KiB |
High-Speed JPEG Video Encoder
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ALSE Igloo nano UART demo |
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466 KiB |
Igloo nano Kit tutorial
|
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ALSE is a Lattice Partner |
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11.5 KiB |
Lattice
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ALSE NAND Controller Flyer |
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177.9 KiB |
NAND Flash Controller
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ALSE Remote Update for Lattice FPGAs |
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926.4 KiB |
Remote Update for Lattice FPGAs
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Altera Design Partner |
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159.5 KiB |
History
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Altera Original Logo |
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7.5 KiB |
History
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Altera Partner |
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58.9 KiB |
Altera
History
|
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AntiCopy |
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41.9 KiB |
Copy Protection
|
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AN_LT24_v2 |
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451.7 KiB |
Using the LT24 / ILI9341
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Arrow AXE5 Eagle board |
|
45.5 KiB |
Agilex 5 FPGAs
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Arrow-Trenz AXE5000 Agilex 5 board |
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190.2 KiB |
Agilex 5 FPGAs
Agilex 5 FPGAs
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Aurora 8B/10B on Lattice Avant |
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1.8 MiB |
Aurora on Avant !
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Aurora 8B/10B Reference Design on Polarfire |
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1.3 MiB |
Aurora 8B/10B on Polarfire
|
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Aurora Typical Application |
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46.1 KiB |
Aurora 8B/10B IP Core
|
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Aurora64 Architecture |
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91.8 KiB |
Aurora 64B/66B IP Core
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AVDB Board |
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136.2 KiB |
AVDB - Video Board (Obsolete)
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AVDB DataSheet |
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1.5 MiB |
AVDB - Video Board (Obsolete)
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AVDB Reference Designs |
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1.1 MiB |
AVDB - Video Board (Obsolete)
|
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AVDB/Clovis User Manual |
|
2.3 MiB |
AVDB - Video Board (Obsolete)
|
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Avnu |
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27.1 KiB |
AVB MILAN
What is AVB MILAN ?
|
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Avnu Alliance |
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11.2 KiB |
Digital Audio
|
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Block diagram of Achilles Arria 10 SoC SOM |
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44.4 KiB |
REFLEX CES DevKits
|
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Block diagram of Alaric Arria 10 SoC |
|
63.1 KiB |
REFLEX CES DevKits
|
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Block diagram of Attila Arria 10 GX |
|
49.6 KiB |
REFLEX CES DevKits
|
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Block diagram of Sargon Stratix 10 GX SX |
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91.4 KiB |
REFLEX CES Stratix 10 boards
|
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block diagram of the COMXpress |
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53.3 KiB |
REFLEX CES Stratix 10 boards
|
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block diagram of the XpressGX/SX S10 |
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82.8 KiB |
REFLEX CES Stratix 10 boards
|
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BlockDiagram |
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52.9 KiB |
MachXO5 Example Design
|
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ChipBridge Datasheet |
ALSE ChipBridge IP Datasheet |
289 KiB |
ChipBridge (Chip-To-Chip)
|
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Colorlight board |
|
1.5 MiB |
LiteX and Lattice FPGAs
|
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Crimson sv |
|
3.3 KiB |
Utilities
|
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Demo Architecture |
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28.8 KiB |
Aurora 64B/66B IP Core
|
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Demo_Agi5_devkit_2026 |
Agilex 5 kit programming and probing files |
2 MiB |
Aurora 64B/66B IP Core
|
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Design Services |
|
33.7 KiB |
ALSE: Advanced Logic Synthesis for Electronics
|
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Ethernet Solutions |
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9.2 KiB |
ALSE: Advanced Logic Synthesis for Electronics
|
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Examples of ALSE Aurora 64 IP on Lattice FPGAs |
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5.8 KiB |
Aurora 64B/66B IP Core
|
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Examples of ALSE Aurora 64 IP on Microchip FPGAs |
|
10.7 KiB |
Aurora 64B/66B IP Core
|
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FloatingPoints_ApNote |
Floating Points in FPGAs Application Note |
425.7 KiB |
Floating Points
|
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FloatingPoints_ApNote |
Floating Points in FPGAs Application Note |
425.7 KiB |
Floating Points in FPGAs
|
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Free IPs |
|
8.8 KiB |
ALSE: Advanced Logic Synthesis for Electronics
|
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GEDEK and I2C Reference Design Manual |
|
1 MiB |
MachXO5 Example Design
|
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GowinFPGA_TEC0117_ApNote |
Gowin TEC0117 Discovery |
181.3 KiB |
Gowin
|
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GraDiEn |
|
32.6 KiB |
Graphic Display
|
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HPAPB DataSheet |
|
1020.5 KiB |
HPAPB - Stratix V
|
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HPAPB Stratix V board |
|
420.2 KiB |
HPAPB - Stratix V
|
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HPBB Board |
|
73.1 KiB |
HPPB - Stratix IV (Obsolete)
|
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HPBBv2 Product Brief |
|
277.1 KiB |
HPPB - Stratix IV (Obsolete)
|
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hyper read |
|
34.9 KiB |
HyperRam Memory Controller
|
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hyper write |
|
30.9 KiB |
HyperRam Memory Controller
|
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Indeex: Industrial Ethernet Extension Board |
|
68.9 KiB |
IndEEx
|
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Industrial Ethernet standards Cycle Time |
|
43.7 KiB |
Ultra Low Latency Network
|
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Install & Discover Lattice Radiant |
|
652.5 KiB |
Discovering Radiant
|
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Intel Agilex 5 FPGA E-Series 065B Development Kit - Premium |
|
207.6 KiB |
Agilex 5 FPGAs
|
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Intel FPGA Design Center |
|
42.3 KiB |
Altera
History
|
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Intellectual Properties |
|
12.4 KiB |
ALSE: Advanced Logic Synthesis for Electronics
|
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Introduction to GEDEK |
|
358 KiB |
Ethernet for FPGA = GEDEK
|
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JESD204B Datasheet |
|
205.8 KiB |
JESD204
|
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JPEG Decoder Datasheet |
|
264.7 KiB |
JPEG Video Decoder
|
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JPEG Encoder Datasheet |
|
333.4 KiB |
JPEG Video Encoder
|
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La Scala Carrier Board (without AVB64M module) |
|
1.1 MiB |
La Scala !
|
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LaScala : MILAN SoM Carrier Board |
|
254 KiB |
AVB MILAN
What is AVB MILAN ?
The ALSE AVB Milan IP
|
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Lattice DSP Application Note #1 |
|
625.1 KiB |
DSP in Lattice FPGAs (1)
|
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LT24 / ILI9341 Application Note |
Shows how to drive an LT24 display from an FPGA. |
358.1 KiB |
Free IPs
|
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LT24 Application Note |
|
451.7 KiB |
Free IPs
|
 |
LVDS 500Mb/s demo using 2 x BeMicroMax10 boards |
|
99.3 KiB |
High Speed LVDS communication
|
 |
LVDS Application Note |
|
541.8 KiB |
High Speed LVDS communication
|
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MachXO5-NX board |
|
46.4 KiB |
MachXO5 Example Design
|
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MachXO5T-NX evaluation board |
|
49.4 KiB |
MachXO5 Example Design
|
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MILAN |
|
204.1 KiB |
AVB MILAN
What is AVB MILAN ?
|
 |
Milan AVB System On Module |
|
63.1 KiB |
AVB MILAN
What is AVB MILAN ?
The ALSE AVB Milan IP
|
 |
Network (ring) Topology |
|
37.7 KiB |
Ultra Low Latency Network
|
 |
Nina extending the DE0-nano |
|
123.8 KiB |
Nina
|
 |
Nina User’s Guide |
|
635.2 KiB |
Nina
|
 |
openPOWERLINK MAX10 |
|
1.1 MiB |
PowerLink
|
 |
Quad SPI Controller Datasheet |
|
376.7 KiB |
Quad SPI Controller
|
 |
Remote Update Application Note |
|
537.2 KiB |
Intel Remote Update Application Note
|
 |
Remote Update Archive |
|
161.9 KiB |
Intel Remote Update Application Note
|
 |
RS232 & UARTs Application Note |
|
165.8 KiB |
Free IPs
|
 |
RS232 & UARTs Basics |
|
167.3 KiB |
UARTs & RS232
|
 |
SelectBadge |
|
94.5 KiB |
|
 |
SelectBadge |
|
92 KiB |
|
 |
SelectBadge |
|
92 KiB |
|
 |
SSRAM no bus latency waveform |
|
196.3 KiB |
Synchronous SRAM (SSRAM) Controller
|
 |
Synchronous Edge Detector |
|
16.1 KiB |
VHDL templates
|
 |
Tower of DE2-115 |
|
192.6 KiB |
Ultra Low Latency Network
|
 |
Typical application |
|
18.1 KiB |
Aurora 64B/66B IP Core
|
 |
VHDL Coding Style Guide |
|
197.1 KiB |
VHDL Coding Guide
|
 |
Formations en France |
|
28 KiB |
ALSE: Advanced Logic Synthesis for Electronics
|