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Format: PNG Untitled 1.1 MiB REFLEX CES DevKits
Format: PNG Untitled 2.1 MiB REFLEX CES DevKits
Format: PNG Untitled 853.3 KiB REFLEX CES Stratix 10 boards
Format: PNG Untitled 1.2 MiB REFLEX CES DevKits
Format: PNG Untitled 1.1 MiB REFLEX CES Stratix 10 boards
Format: PNG Untitled 999.6 KiB REFLEX CES Stratix 10 boards
Format: PNG Untitled 42.5 KiB Aurora 64B/66B IP Core
Format: JPEG Untitled 53.2 KiB Happy New Year
Format: PDF 10GEDEK Datasheet 232.8 KiB 10G Ethernet for FPGAs
Format: PNG ADM Block Diagram 72.1 KiB ADM - Max 10
Format: PDF ADM DataSheet 322.5 KiB ADM - Max 10
Format: JPEG ADM Max 10 Module 220.2 KiB ADM - Max 10
Format: JPEG AES member 17.6 KiB Digital Audio
Format: PNG Agilex 257.3 KiB Designing for Stratix 10 & Agilex FPGAs
Format: PDF ALSE 10GEDEK IP Reference Design on Polarfire 701 KiB 10G Ethernet on Polarfire
Format: PDF ALSE : a Short Presentation ALSE Short presentation 2.9 MiB ALSE: Advanced Logic Synthesis for Electronics
Format: PDF ALSE AntiCopy solution 578.4 KiB Copy Protection
Format: PDF ALSE Aurora 64B/66B Reference Design for Polarfire 596.4 KiB Aurora 64B/66B IP Core on Polarfire
Format: PDF ALSE Aurora 8B/10B Datasheet 439.6 KiB Aurora 8B/10B IP Core
Format: PDF ALSE Aurora64 Agilex5 Demo User Guide 3.2 MiB Aurora 64B/66B IP Core
Format: PDF ALSE Aurora64 Demo on Efinix Titanium 1.2 MiB ALSE Aurora 64B/66B on Efinix
Format: PDF ALSE Aurora8b10b on Efinix Titanium : Demo User Guide 1.6 MiB ALSE Aurora 8B/10B on Efinix
Format: JPEG ALSE HighSpeed (dual-core) JPEG Encoder 90.3 KiB High-Speed JPEG Video Encoder
Format: PDF ALSE Igloo nano UART demo 466 KiB Igloo nano Kit tutorial
Format: JPEG ALSE is a Lattice Partner 11.5 KiB Lattice
Format: PDF ALSE NAND Controller Flyer 177.9 KiB NAND Flash Controller
Format: PDF ALSE Remote Update for Lattice FPGAs 926.4 KiB Remote Update for Lattice FPGAs
Format: JPEG Altera Design Partner 159.5 KiB History
Format: PNG Altera Original Logo 7.5 KiB History
Format: PNG Altera Partner 58.9 KiB Altera
History
Format: JPEG AntiCopy 41.9 KiB Copy Protection
Format: PDF AN_LT24_v2 451.7 KiB Using the LT24 / ILI9341
Format: JPEG Arrow AXE5 Eagle board 45.5 KiB Agilex 5 FPGAs
Format: JPEG Arrow-Trenz AXE5000 Agilex 5 board 190.2 KiB Agilex 5 FPGAs
Agilex 5 FPGAs
Format: PDF Aurora 8B/10B on Lattice Avant 1.8 MiB Aurora on Avant !
Format: PDF Aurora 8B/10B Reference Design on Polarfire 1.3 MiB Aurora 8B/10B on Polarfire
Format: PNG Aurora Typical Application 46.1 KiB Aurora 8B/10B IP Core
Format: JPEG Aurora64 Architecture 91.8 KiB Aurora 64B/66B IP Core
Format: JPEG AVDB Board 136.2 KiB AVDB - Video Board (Obsolete)
Format: PDF AVDB DataSheet 1.5 MiB AVDB - Video Board (Obsolete)
Format: PDF AVDB Reference Designs 1.1 MiB AVDB - Video Board (Obsolete)
Format: PDF AVDB/Clovis User Manual 2.3 MiB AVDB - Video Board (Obsolete)
Format: JPEG Avnu 27.1 KiB AVB MILAN
What is AVB MILAN ?
Format: JPEG Avnu Alliance 11.2 KiB Digital Audio
Format: PNG Block diagram of Achilles Arria 10 SoC SOM 44.4 KiB REFLEX CES DevKits
Format: PNG Block diagram of Alaric Arria 10 SoC 63.1 KiB REFLEX CES DevKits
Format: PNG Block diagram of Attila Arria 10 GX 49.6 KiB REFLEX CES DevKits
Format: PNG Block diagram of Sargon Stratix 10 GX SX 91.4 KiB REFLEX CES Stratix 10 boards
Format: PNG block diagram of the COMXpress 53.3 KiB REFLEX CES Stratix 10 boards
Format: PNG block diagram of the XpressGX/SX S10 82.8 KiB REFLEX CES Stratix 10 boards
Format: JPEG BlockDiagram 52.9 KiB MachXO5 Example Design
Format: PDF ChipBridge Datasheet ALSE ChipBridge IP Datasheet 289 KiB ChipBridge (Chip-To-Chip)
Format: JPEG Colorlight board 1.5 MiB LiteX and Lattice FPGAs
Format: 7 Zip Crimson sv 3.3 KiB Utilities
Format: PNG Demo Architecture 28.8 KiB Aurora 64B/66B IP Core
Format: Zip Demo_Agi5_devkit_2026 Agilex 5 kit programming and probing files 2 MiB Aurora 64B/66B IP Core
Format: JPEG Design Services 33.7 KiB ALSE: Advanced Logic Synthesis for Electronics
Format: GIF Ethernet Solutions 9.2 KiB ALSE: Advanced Logic Synthesis for Electronics
Format: PNG Examples of ALSE Aurora 64 IP on Lattice FPGAs 5.8 KiB Aurora 64B/66B IP Core
Format: PNG Examples of ALSE Aurora 64 IP on Microchip FPGAs 10.7 KiB Aurora 64B/66B IP Core
Format: PDF FloatingPoints_ApNote Floating Points in FPGAs Application Note 425.7 KiB Floating Points
Format: PDF FloatingPoints_ApNote Floating Points in FPGAs Application Note 425.7 KiB Floating Points in FPGAs
Format: GIF Free IPs 8.8 KiB ALSE: Advanced Logic Synthesis for Electronics
Format: PDF GEDEK and I2C Reference Design Manual 1 MiB MachXO5 Example Design
Format: PDF GowinFPGA_TEC0117_ApNote Gowin TEC0117 Discovery 181.3 KiB Gowin
Format: PNG GraDiEn 32.6 KiB Graphic Display
Format: PDF HPAPB DataSheet 1020.5 KiB HPAPB - Stratix V
Format: JPEG HPAPB Stratix V board 420.2 KiB HPAPB - Stratix V
Format: JPEG HPBB Board 73.1 KiB HPPB - Stratix IV (Obsolete)
Format: PDF HPBBv2 Product Brief 277.1 KiB HPPB - Stratix IV (Obsolete)
Format: PNG hyper read 34.9 KiB HyperRam Memory Controller
Format: PNG hyper write 30.9 KiB HyperRam Memory Controller
Format: JPEG Indeex: Industrial Ethernet Extension Board 68.9 KiB IndEEx
Format: JPEG Industrial Ethernet standards Cycle Time 43.7 KiB Ultra Low Latency Network
Format: PDF Install & Discover Lattice Radiant 652.5 KiB Discovering Radiant
Format: JPEG Intel Agilex 5 FPGA E-Series 065B Development Kit - Premium 207.6 KiB Agilex 5 FPGAs
Format: PNG Intel FPGA Design Center 42.3 KiB Altera
History
Format: GIF Intellectual Properties 12.4 KiB ALSE: Advanced Logic Synthesis for Electronics
Format: PDF Introduction to GEDEK 358 KiB Ethernet for FPGA = GEDEK
Format: PDF JESD204B Datasheet 205.8 KiB JESD204
Format: PDF JPEG Decoder Datasheet 264.7 KiB JPEG Video Decoder
Format: PDF JPEG Encoder Datasheet 333.4 KiB JPEG Video Encoder
Format: JPEG La Scala Carrier Board (without AVB64M module) 1.1 MiB La Scala !
Format: JPEG LaScala : MILAN SoM Carrier Board 254 KiB AVB MILAN
What is AVB MILAN ?
The ALSE AVB Milan IP
Format: PDF Lattice DSP Application Note #1 625.1 KiB DSP in Lattice FPGAs (1)
Format: PDF LT24 / ILI9341 Application Note Shows how to drive an LT24 display from an FPGA. 358.1 KiB Free IPs
Format: PDF LT24 Application Note 451.7 KiB Free IPs
Format: JPEG LVDS 500Mb/s demo using 2 x BeMicroMax10 boards 99.3 KiB High Speed LVDS communication
Format: PDF LVDS Application Note 541.8 KiB High Speed LVDS communication
Format: JPEG MachXO5-NX board 46.4 KiB MachXO5 Example Design
Format: JPEG MachXO5T-NX evaluation board 49.4 KiB MachXO5 Example Design
Format: JPEG MILAN 204.1 KiB AVB MILAN
What is AVB MILAN ?
Format: JPEG Milan AVB System On Module 63.1 KiB AVB MILAN
What is AVB MILAN ?
The ALSE AVB Milan IP
Format: JPEG Network (ring) Topology 37.7 KiB Ultra Low Latency Network
Format: JPEG Nina extending the DE0-nano 123.8 KiB Nina
Format: PDF Nina User’s Guide 635.2 KiB Nina
Format: PDF openPOWERLINK MAX10 1.1 MiB PowerLink
Format: PDF Quad SPI Controller Datasheet 376.7 KiB Quad SPI Controller
Format: PDF Remote Update Application Note 537.2 KiB Intel Remote Update Application Note
Format: Zip Remote Update Archive 161.9 KiB Intel Remote Update Application Note
Format: PDF RS232 & UARTs Application Note 165.8 KiB Free IPs
Format: PDF RS232 & UARTs Basics 167.3 KiB UARTs & RS232
Format: PNG SelectBadge 94.5 KiB
Format: JPEG SelectBadge 92 KiB
Format: JPEG SelectBadge 92 KiB
Format: JPEG SSRAM no bus latency waveform 196.3 KiB Synchronous SRAM (SSRAM) Controller
Format: JPEG Synchronous Edge Detector 16.1 KiB VHDL templates
Format: JPEG Tower of DE2-115 192.6 KiB Ultra Low Latency Network
Format: PNG Typical application 18.1 KiB Aurora 64B/66B IP Core
Format: PDF VHDL Coding Style Guide 197.1 KiB VHDL Coding Guide
Format: JPEG Formations en France 28 KiB ALSE: Advanced Logic Synthesis for Electronics
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