Definitions

Abbreviations

ASIC

Application Specific Integrated Circuit. It is a Custom Design chip implementing usually many functions and designed by a customer. As opposed to Programmable devices or to ASSPs.

ASSP

(from Wiki) an Application Specific Standard Product is an integrated circuit that implements a specific function that appeals to a wide market (examples are microprocessors, DSPs, various controllers etc). ASSPs are available as off-the-shelf components.

AVDB

Advanced Video Development Board (Cyclone V board designed by ALSE for Video applications).

BAYER

A Bayer filter is a mosaic (color filter array = CFA) for distributing Red Green and Blue color filters across a square grid of photosensors.

CFA

Color Filter Array. A mosaic of alternating Red-Green-Blue filters to capture color images by sub-sampling with a sensor. The final image has to be reconstructed to interpolate the missing information. Different layouts are used.

CPLD

Complex Programmable Logic Devices. Typically smaller than FPGAs and do not require an external configuration memory.

Demosaicing

aka De-Bayer, or CFA Filter : interpolates RGB values for each pixel on sensors who only deliver one color per pixel (like through a Bayer filter).

DisplayPort

Digital and packet-based Display interface (royalty-free and developed by VESA) to connect a video source to a display device.
Typically competing against HDMI.

EDID

Extended Display Identification Data (by VESA).
Allows the receiver (TV or Display) to disclose to the source (Graphic card, Player…) the video (and audio) formats it does support.

FPGA

Field Programmable Gate Array.
Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.

GEDEK

Gigabit Ethernet Data Exchange Kit. “Hardware Stack” Concept invented by ALSE, GEDEK is a processor-less autonomous block which implements the Ethernet protocols required to establish, maintain, and perform high performance data exchange over standard Ethernet.

HDCP

High-bandwidth Digital Content Protection.
See the Wikipedia article.

HDL

Hardware Description Language.
Some HDLs are : Verilog, SystemVerilog, VHDL, SystemC.
First-generation (now obsolete) HDLs : Abel, CUPL etc

HDMI

High Definition Multimedia Interface. Most widely used version is 1.4, but 2.0 starts becoming available (also as FPGA IP).

HPAPB

High Performance Acquisition and Processing Board : 8-channels Stratix V Signal Acquisition and Processing Board designed by ALSE.

HPPB

High Performance Base Board. Stratix IV Signal Acquisition and Processing board, designed by ALSE.

ILT

Instructor-Led Training, delivered by a live Instructor interacting directly with the students. As opposed to self-paced trainings.

IP

Intellectual Property. A usually complex function developed, tested and sold off-the-shelf to be re-used in customer’s designs. Ranges from Processor cores to Memory Controllers to Video processing blocks etc… Some IPs are available from the FPGA vendor (free or at cost) or from 3rd parties.

LRM

Language Reference Manual. The “bible” of the language, which completely defines the standard.

MAC

Media Access Controller. The Ethernet (802.3) MAC block is connected to the Media Interface of the Ethernet PHY (the PHYsical transceiver chip) in order to send and receive streams of bytes.

PCB

Printed Circuit Board. A key and potentially extremely complex piece in any project.

PHY

PHYsical Interface. Device in charge of handling (encoding and decoding) the lowest layer of the protocol (the physical signals).
In case of Ethernet, the PHY chip is connected to the magnetics & RJ45 on one side, and offers a normalized data interface (MII, GMII, RGMII, SGMII etc).

PSL

Property Specification Language.
Normalisé as IEEE 1850 and now part of VHDL-2008, thus language allows describing Properties and Assertions, thus enabling the ABV (Assertion Based Verification) methodology.
A (roughly) equivalent to PSL can be found in SystemVerilog as “SVA”.

RTL

Register Transfer Level. Simply put: it’s HDL code that is suitable for synthesis. Which mean in practice describing what happens on rising edges of a Clock.

SERDES

SERializer - DE-Serializer. See Wikipedia.
Most recent FPGAs now offer a number of SERDESes allowing to stream data in and out of the FPGA serially at very high speeds. Moreover, recent connectivity protocols like PCIExpress, HDMI, DisplayPort etc make use of SERDESes.

SOC

System On Chip. Usually a chip that contains one (or several) microprocessors on the die, as well as other logic. A SOC-FPGA is an FPGA that has Hard Core Processor(s) tied to the programmable logic.

SystemVerilog

SystemVerilog (IEEE standard 1800) is an HDVL (Hardware Description & Verification Language).
This is the Language that now supersedes both Verilog and VHDL, thus becoming the de facto Language of the next 20 years.

UVM

Universal Verification Methodology. The convergence of many different vendor-specific Methodologies and the only one that is here to stay. It is based on SystemVerilog and especially the Classes (OOP) part of it. UVM is hard to learn and master.

Verilog

The first (in order of appearance) Hardware Description Language (like VHDL which followed a few years later). Normalized as IEEE 1364.

VHDL

VHSIC Hardware Description Language.
A consequence of the US DOD’s VHSIC program, this language (normalized as IEEE 1076) was created to describe accurately the behavior of High Speed Integrated Circuits.

VHSIC

Very High Speed Integrated Circuits.
US Program (DOD) in the 80s to develop High Speed Logic Circuits.

VIP

Altera Video IP suite. A collection of IP blocks for Video Applications.