Aurora 64B/66B is a lightweight and open protocol suitable for chip-to-chip, board-to-board and backplane applications using very high speed transceivers.

The ALSE Aurora 64B/66B IP core is a very compact and optimized implementation of this protocol, also developed and verified to ensure full compatibility with the Xilinx IP core (interoperability has been tested and demonstrated).

This IP is available on all the high-end Altera/Intel FPGAs (from Stratix V and Cyclone10gx to Agilex-7 and Agilex-5), but also for all other FPGA vendors including Lattice, Microchip and Efinix.

Last but not least, we have developed and delivered an ASIC version of our IP !

Compared to the 8B/10B version of the Aurora protocol, the 64B/66B flavor addresses the highest lanes speeds (when 8B/10B typically stops at 6 GBs per lane).
It also offers an effective bandwidth of up to 97%, instead of 80% for 8B/10B.

Our Aurora64B/66B IP therefore provides an efficient way to interconnect Altera/Intel, Xilinx, Lattice, Microsemi/Microchip and finix FPGAs, or any other chip (ASIC, ASSP, etc …) using the public Aurora 64B/66B protocol.