JPEG Video Decoder

This compact and extremely efficient core is capable of decoding in real-time video on-the-fly using standard and ubiquitous JPEG compression, even on low-cost FPGAs.
This IP does not require any processor nor any external memory.


Our Baseline JPEG Decoder (Decompression) core is capable of decoding JPEG-compressed video on-the-fly and produce raw video stream.

For streaming decoding of High Resolution (like Full-HD) on low cost FPGAs, two decoders in parallel may be used.

Easy to use

Our core is compact and implements standard interfaces, so it can be used easily either as a standalone block, or as part of a Qsys system. Again : it does not require any embedded processor. It is small and efficient enough to fit easily in low cost and small FPGAs (like Cyclone V). With two instances working in parallel, it is possible to decode Full-HD in real time.

The core can be used as a stand-alone block or with Qsys, with or without the Altera Video IP suite (“VIP”).

Our simulation environment can be helpful to develop and the application that includes the JPEG decoder.

This core has been used (with the corresponding JPEG Encoder) in a very successful consumer product.

This IP core is also used in many Demos and Reference Designs that are available with ALSE’s AVDB Video board. In many cases, purchasing an AVDB board to develop or to prototype the application will make a lot of sense.

Main Technical characteristics

  • Speed and Area-Optimized engine suitable for both still image and real-time video compression.
  • 8 bits (byte) Streaming input interface with Backpressure. Easy to connect to the ALSE Ethernet communication engine for example.
  • Standard Huffman table.
  • Dynamic Quantization tables extracted automatically from the input stream
  • Versatile. This IP can be used in most FPGA families (internal memory blocks must be available).
  • Compact. On an Altera Device, the area is typically less than 3500 Logic Elements, 5 memory blocks and 9 DSP18-bits (multipliers) are used.
  • Fast : on an old Altera EP3C25F256C6 Cyclone III Device, the Decoder can run at more than 180 MHz.
  • First-class Technical Support (E-mail and Telephone, extended CET hours).
  • Customization to specific needs available.

Best in class

Some ALSE IPs also exist in the competition, JPEG Decoder is in this case. However, our IP offers unique characteristics and advantages.

  • More compact.
  • More efficient than the competition.
  • Faster.

Demos available

We have many demos created for several FPGA boards, including our AVDB Video Development Board.

Information available

A datasheet is available, but do not hesitate to contact us if you want more details.

ALSE demo : Streaming Full-HD on PowerLines
HDMI -> JPEG Encoder -> GEDEK -> Ethernet -> GEDEK -> JPEG Decoder -> HDMI

Document download

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