SRAM Controller

A.L.S.E has developed a very compact and efficient Static RAM controller that can be easily integrated in any FPGA project.

Main Technical Features

  • High-Performance Controller supporting Burst Mode for Read/Write transfers, to get optimized transfer speed and minimal switch fabric overhead.
  • Asynchronous interface management with fastest Memory timings, depending FPGA and Memory speed grades, and Customer board Timing Constraints.
  • 16/32bits Slave Interface (Avalon-MM based) with Burst support. Typically, the Controller will serve a Master that can be an Altera Nios II CPU (32bits), with or without Caches, with or without Burst mode. A hardware master (DMA) is of course also possible.
  • Generic for different SRAM memory densities (address bus) and data bus size
  • Versatile. This IP can be used in all FPGA devices (Altera, Xilinx, Lattice, MicroSemi Actel) having internal memory blocks (CPLDs not supported).
  • Easy integration in Altera Qsys or manually (non-SOPC designs).
  • Comes with sophisticated SDC Timing Constraints, and Hardware Tester Reference Design.

This controller replaces the tri-state bridge. It provides high performance enhancement, as well as a reliable interface (checked and optimized with SDC constraints).