Obsolescence Mitigation

If you are facing the problem of dealing with Obsolete parts and boards (due to ROHS requirements or totally obsolete and unavailable components), then you may quickly fall in love with FPGAs, if you’re not already an adept !

Typical “complex” parts from the 80s, like CPUs and indeed Peripherals end up as fitting nicely in small and cheap FPGAs… provided that you find the HDL code (the IP) for the re-designed function(s).

But the problem doesn’t stop here ! You’ll soon discover that you’ll need also:

  • Obsolete external memories
  • Obsolete Peripherals
  • Obsolete glue logic
  • To deal with the damned 5V Vcc issue…
  • all this likely within a tight budget, and a short deadline.

In fact, the solution is to re-design the entire board in one single FPGA !
And this is perfectly realistic. Since FPGAs are now extremely dense and fast, they have no problem embedding most if not all the logic for the whole board and sometimes even the reasonable amount of RAM of old pre-Microsoft (read: frugal & no-nonsense) systems. Moreover, obsolete non-volatile memories can easily be emulated by cheap (and faster) modern memories (like Serial Flash memories).

Of course, doing this sounds simple, but it demands a certain know-how and access to a good quality synthesizable model for the CPU. High quality IPs exist, with the price tag that comes along, but there is also some affordable or almost free IPs developed by (usually gifted) enthusiasts. This path is more dangerous than renowned IP providers and the apparent gain can become a dead end, but with sufficient know-how and an active community behind some projects, this is a more and more viable solution.

Once you’ve found a good synthesizable IP for the CPU, you’re not quite out of the woods yet. You’ll need also to:

  • Analyze the complete board (which may even include some old programmable parts -like PALs/GALs-, sometimes with lost description !)
  • Find good quality models for the Peripherals (same problem as for the CPU) or:
  • Analyze how the Peripherals were used and re-code only the required functions. We have done this several times, and it is a very efficient solution !
  • In the following pages, you’ll see some of the peripherals that we have redesigned in this context.
    Let’s suppose you have addressed all the issues above. One question remains:
    How are you going to test your new design ?
    This may seem a tough challenge since all the logic, busses, ChipSelects etc are now internal to the FPGA, and therefore unobservable ?
    Why, it’s simply not the case ! In fact, most modern FPGA Design tools offer In-System debugging and Logic Analysis. With Altera for example, these tools are powerful, easy to use, and free, even with the free version of Quartus. You can observe and modify internal memories in real time ! You can put a logic analyzer inside the CPU, etc… All things that were impossible in the past.
    Note that some commercial CPU IPs include an OCD feature (On-Chip-Debug) so the debug tools can end up being better than the original ones.

You can take a look at the articles in this section (menu on the left) in which you will see Asic to FPGA, 6809, Z803-8530, 8254, PCA9556-9557

If you are facing Obsolescence issues, contact ALSE.
We have solved similar problems in the past, very quickly and cost-effectively.