We have developed a limited RTL model of the Zilog Z8030/8530 - SCC Serial Communication Chip. We used it in combination with the model of the obsolete 6809 CPU to re-design an obsolete industrial board into an FPGA.

Our model is currently not exhaustive: we have only modeled the UART (Asynchronous Serial communication functions) but not the Synchronous part. In other words, if your design uses the Synchronous mode, we don’t have the right model off-the-shelf.

It’s typically easy to verify how the chip was used and make sure the RTL model will behave adequately.

The features of our IP are :

  • Two Independent, 0 to 2M Bits/Second, Full Duplex Channels, each with a Separate Baud Rate Generator (see below about ext osc emulation).
  • Asynchronous Mode with 5 to 8 Data Bits and 1, 1.5, or 2 Stop Bits per character,
  • Programmable Clock Factor, Break Detection and Generation, Parity, Overrun, and Framing Error Detection. Three interrupts are implemented.
  • Local Loopback and Auto Echo Modes
  • Fully synchronous implementation.
  • Emulation of the external oscillators using the internal clock source (removes the need for external oscillators).
  • Same register Set as the original part for software compatibility (in Asynchronous communication mode).
  • Deliverables include complete RTL source code (VHDL) with test benches and behavioral models.

If you are interested in this model, let us know, we could complete it if necessary for your project.