Asic to FPGA

In some cases, you may have an old ASIC that becomes obsolete. You cannot afford to redesign a similar ASIC, yet you would like to avoid redesigning the complete system(s) that were using it.
Another case is wanting to include the functions performed by an obsolete ASIC into a new design. _A possible solution to this kind of problems is to use what you can recover from the original ASIC specification and design an FPGA based on this.

At ALSE, we’ve performed this kind of job quite a few times already.

In some cases, a lot of the original ASIC specification was lost (but we got high level description and a netlist) , at other times we had more complete functional description as well as expected values based on known stimuli.

These projects were not trivial but all successful in the end. In one case, a tweaking phase was necessary to painfully re-create the bugs and limitations of the original ASIC (!) since they contributed to create enormous databases of data that were exploited by sophisticated algorithms that took into account the ASIC exact behavior.

It is certainly not among our most typical projects, but we’ve been there, done that ;-)