Aurora 8b/10b IP Core

Aurora 8b/10b IP Core

The Aurora 8b/10b IP Core is a lightweight high-speed serial protocol suitable for chip-to-chip, board-to-board and backplane applications using high speed transceivers.
For Xilinx users, Aurora is available as a Xilinx Logicore IP.
Our IP makes Aurora available to ASICs and to other FPGAs, including of course Intel-FPGAs (formerly Altera).
Our IP provides an efficient way to interconnect an Intel-FPGA and a Xilinx FPGA, or any other chip (ASIC, ASSP, etc …) using the Aurora protocol. It can even be used to interconnect two Intel-FPGAs together, in replacement of other proprietary or complex High-Speed Serial protocols (like Serial Lite 3 or PCIExpress).
The Figure below shows a typical application of the IP :

Aurora Typical Application - PNG - 59.5 kb
Aurora Typical Application
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Main Aurora-Protocol Supported Features

  • Full-Duplex and Simplex Tx Operations.
  • Currently demonstrated at up to 6.6 Gbps (Gigabits per seconds) per Transceiver lane. Higher bitrates are possible depending on the Device Transceiver characteristics.
  • Up to 16 Transceiver lanes.
  • Framing and Streaming interface.
  • Payload Data User Frames (PDU)
  • User Flow Control (UFC).
  • Native Flow Control (NFC), in immediate and completion mode.
  • Additional CRC for PDU Frames
  • 8b/10b Encoding / Decoding.
  • Clock Compensation sequence generation.
  • Per lane polarity inversion and skew compensation.
  • User datapath depending on number of lanes and 16bits/32bits mode per Transceiver lane. Examples :
    -> in a x1 /32bits configuration, the user datapath is 32bits.
    -> in a x4 /32bits configuration, the user datapath is 128bits.
    -> in a x4 /16bits configuration, the user datapath is 64bits.

Not (yet) supported :

  • Simplex Rx Operation
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Other Technical Features

  • Most recent Intel-FPGAs are supported : Arria 10, Stratix V, Arria V, Cyclone V. For other Altera / Intel families, or for any other FPGA vendor (e.g : Lattice), please contact ALSE.
  • AXI streaming / Avalon-ST compatible for User interfaces (PDU, NFC, UFC)
  • Very low FPGA resource usage : typically less than 1000 ALMs / 2 Memory Blocks for a Full IP in a x1 (1 lane) configuration
  • Provided with SDC Timing Constraints and QIP file for easy integration
  • Hardware Tester Reference Designs
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Examples of existing Hardware Tester Reference Designs

  • CycloneV Clovis -> Xilinx Virtex6 ML605, x1 - 3.125Gbps
  • CycloneV Clovis -> Xilinx Virtex7 VC707, x1 - 3.125Gbps
  • Arria10 Attila -> Xilinx Virtex7 VC707, x1 - 6.25Gbps
  • Arria10 Achilles -> Arria10 Attila, x4 - 6.25Gbps
  • etc …

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