HyperBus / HyperRam Memory Controller

The new HyperRAM memories, based on low-power PSRAM technology and using a newly defined HyperBus interface, are a very welcome addition to the traditional RAM memories portfolio : they have been optimized for Mobile and Automotive applications and are an excellent fit for many projects.

  • They provide good Bandwidth performance
  • The interface, known as “HyperBus”, offers a low signal count (Address, Command and Data using only eight DQ pins)
  • They offer Low Power consumption
    Typical power consumption during burst read is about 60 mA only.
  • User-friendly protocol, with Hidden Refresh mode, for example
  • Most devices are available for Automotive Temperature range…

ALSE has designed a very-low resource usage HyperBus Memory Controller, in order to provide an easy interface to the HyperRAM memories, along with high performance (up to 333 MBytes/s, which is 1.5 x times faster than a 16 bits PSRAM running at 108MHz).

Main Technical Features

  • High-Performance HyperBus Controller supporting Burst Mode for Read/Write transfers, to get optimized bandwidth and minimal switch fabric overhead.
  • Memory Operating Frequency typically up to 166 MHz, depending on FPGA and Memory speed grades, and (more marginally) on the customer PCB. This delivers a bandwidth up to 333 MBytes/s, with only 12 x IO pins (CS, Clk/Clk_n, DQS, DQ[7:0])
  • 16 bits Slave Data Interface with Burst support.
  • _ Typically, the Controller will serve a Master that can be an Altera Nios II CPU, with or without caches, with or without Burst mode. A hardware master (like a DMA) is of course also possible (e.g : Video streaming DMAs, etc…)
  • 16 bits Slave Register Interface to access HyperRAM memory registers (for configuring Output Drive Strength, Burst Wrap, etc…)
  • Very low FPGA resource usage : less than 200 x Logic Cells, and 2 x Memory Blocks
  • Versatile : this IP can be used in all FPGA devices (Intel / Altera, Xilinx, Lattice, MicroSemi / Actel) that have internal memory blocks.
  • Intel Qsys (Platform Designer) compliant
  • Provided with sophisticated SDC Timing Constraints, Hardware Tester Reference Designs on FPGA Dev Kits :
  • Tested on the Xilinx Artix7 Trenz TE0725 kit
  • Tested on the Intel Cyclone 10 LP FPGA Evaluation Kit

Typical waveforms

Here is above a typical waveform of a Write access, with initial Latency.

hyper write - PNG - 30.9 kb
hyper write

Here is above a typical waveform of a Read accesses, with initial Latency.

hyper read - PNG - 34.9 kb
hyper read

Examples of supported Memories

  • ISSI IS66/67WVH8M8ALL/BLL - 64Mb
  • Cypress S27KL/S0641 - 64Mb
  • Cypress S70KL/S1281 - 128Mb
  • etc …