HyperBus / HyperRam Memory Controller

The new HyperRAM memories, based on low-power PSRAM technology and using a newly defined HyperBus interface, are a very welcome addition to the traditional RAM memories portfolio : they have been optimized for Mobile and Automotive applications and are an excellent fit for many projects.

  • They provide good Bandwidth performance
  • The interface, known as “HyperBus”, offers a low signal count (Address, Command and Data using only eight DQ pins)
  • They offer Low Power consumption
    Typical power consumption during burst read is about 60 mA only.
  • User-friendly protocol, with Hidden Refresh mode, for example
  • Most devices are available for Automotive Temperature range…

ALSE has designed an extremely efficient and versatile HyperBus Memory Controller. It provides an easy interface to the HyperRAM memories, with maximum performance (up to 333 MBytes/s, which is 1.5 x times faster than a 16 bits PSRAM running at 108 MHz). It is also extremely reliable while being compact. Our customers have compared and report our controller as a clear winner.

Main Technical Features

  • High-Performance HyperBus Controller supporting Burst Mode for Read/Write transfers, to get optimized bandwidth and minimal switch fabric overhead.
  • Memory Operating Frequency typically up to 166 MHz, depending on FPGA and Memory speed grades, and (more marginally) on the customer PCB. This delivers a bandwidth up to 333 MBytes/s, with only 12 x IO pins (CS, Clk/Clk_n, DQS, DQ[7:0])
  • 16 bits Slave Data Interface with Burst (and wrap) support. Typically, the Controller will serve a Master that can be an Altera Nios II or another CPU, with or without caches, with or without Burst mode.
    Other hardware masters (like DMA engines) are of course also possible (e.g : Video streaming DMAs, SGDMAs etc…)
  • 16 bits Slave Register Interface to access HyperRAM memory registers (for configuring Output Drive Strength, Burst Wrap, etc…)
  • Burst Wrap mode support (for efficient transfer with caches).
  • Very low FPGA resource usage (Logic Cells and Memory Blocks)
  • Versatile : this IP can be used in all FPGA devices (Intel / Altera, Xilinx, Lattice, Microchip / MicroSemi / Actel) that have internal memory blocks.
  • Intel Qsys (Platform Designer) compliant, with an advanced configuration panel.
  • Highly configurable. A lot of options and settings are available to parameterize and optimize the controller.
  • Provided with sophisticated SDC Timing Constraints.
  • Comes with advanced Hardware Tester Reference Designs in source code. Allows to test and qualify custom boards . The testers are ready to use for several FPGA Design Kits :
  • Tested on the Xilinx Artix7 Trenz TE0725 kit
  • Tested on the Intel Cyclone 10 LP FPGA Evaluation Kit
  • NEW ! Supports dual-die HyperRam chips !
  • NEW ! AXI4 support for Xilinx
  • COMING ! Microsemi/Microchip PolarFire support.

Typical waveforms

Here is above a typical waveform of a Write access, with initial Latency.

hyper write

Here is above a typical waveform of a Read accesses, with initial Latency.

hyper read

Examples of supported Memories

  • ISSI IS66/67WVH8M8ALL/BLL - 64Mb
  • Cypress S27KL/S0641 - 64Mb
  • Cypress S70KL/S1281 - 128Mb
  • etc …
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